Have you ever wondered how system and methods fail to fulfill the required needs? We need to find a solution to the interruptions in a multi-processer computer.

One embodiment relates generally to computers and, more particularly, to a interrupt handling technique for a multi-processor computer.

Abstract

Most computers can support various components and devices that comprise or interface with the computer in a variety of different ways. These components and devices must be supported by different software programs and operating environments running in the computer.

Illustrations

For example, a personal computer may connect to peripheral devices through one or more peripheral buses or ports. Examples of popular peripheral buses include a universal serial bus ("USB") or an IEEE 1394 serial bus ("1394 bus"). The USB is a two-wire serial personal computer bus, designed by a consortium of computer makers and suppliers, which can support many peripheral devices either in parallel or in a daisy chain configuration. The 1394 bus is also a two-wire serial personal computer bus, very similar to the USB. Specifications for the 1394 bus are available from the Institute of Electrical and Electronics Engineers, Inc. ("IEEE"), 345 East 47th Street, New York, N.Y. 10017-2394. For both the USB and the 1394 bus, when a device is connected to the bus, it provides a predetermined code that identifies its type and bandwidth requirements.

Problems occur when a computer implements an operating environment that is not aware of a specific type (e.g., does not provide appropriate device drivers) of device. To resolve these problems, the computer must implement device support outside of the operating environment. For example, if a computer uses a USB port for a USB keyboard while implementing a PS/2 operating environment (a PS/2 operating environment expects a PS/2 type keyboard), the computer's basic input/output system ("BIOS") can intercept data and software access to and from specific ports associated with the keyboard. The BIOS thereby "translates" the commands between the newer USB keyboard and the operating environment for use with older (or "legacy") keyboards by examining the internal processor ports and registers and "routing" data accordingly.

Continuing with the present example, if the processor writes a data value to port 60h (60 hexadecimal, which is a port defined for use by a PS/2 keyboard), the write instruction causes a system management interrupt ("SMI") trap. In response to the SMI trap, the BIOS instructs the processor to enter a system management mode. The BIOS then places the appropriate data in the processor's registers.

Similarly, the BIOS can be interrupted in order to be requested to go into standby mode. In order to determine what the BIOS was interrupted for, the BIOS must inspect the software instructions. The BIOS relies on data stored in the processor registers to determine this. The BIOS should then retrieve the appropriate data out of the processor's registers to make a decision or perform an action.

However, the BIOS may be interrupted for several reasons and may not be able to determine the reason from the hardware or the interrupt alone. A problem exists when the computer has multiple processors. In these computers, the BIOS has no way to know which of the processors in the multiprocessor system initiated the request. In the above-described examples, the BIOS must determine which of the processors instruction execution caused the interrupt to properly route the data to or from the USB keyboard.

Therefore, what is needed is a system and method for handling system management interrupts in a multiprocessor computer.

In response to the aforementioned problems, a technical advance is achieved by a system and method for handling interrupts in a multiprocessor computer. In one embodiment, the method handles one or more system management interrupts caused by one or more of the processors in the multiprocessor computer system. When a system management interrupt occurs, the computer enters system management mode and the processors store the contents of their registers in memory. The method checks the register contents stored in memory to find the actual physical location of desired data such as an opcode. The method fetches and examines the opcode indicated by the register contents. If the opcode is of the type that would cause a system management interrupt, such as a read or write to port 60h (hexadecimal) or 64 h, this indicates that the current processor is the one to receive the interrupt.

The opcodes may be read or write operations to ports that are not currently being used by existing components. For example, PS/2 keyboards often use ports 60h and 64 h for read and write operations. If the computer is running a program that only supports PS/2 keyboards, yet the computer itself has a USB keyboard, then the computer must translate and route data to the appropriate processor registers for the accesses to and from these ports.

In some embodiments, relative addressing is used by one or more of the processors. As a result, the method must also translate the relative address to an actual physical address in order to locate an operating instruction indicated by the register.

DESCRIPTION OF A PREFERRED EMBODIMENT

Referring to FIG. 1, the reference numeral 10 designates, in general, a computer for implementing several different embodiments. The computer 10 is illustrated with many different components, it being understood that many of the components may be used by some embodiments and not by other embodiments. Actual component types are also discussed for the sake of example, it being further understood that a wide variety of substitution is expected for different embodiments.

The computer 10 includes two processors 12a, 12b, which may for example be Pentium II processors from Intel, Corp. of Santa Clara, Calif. and capable of supporting an operating system such as Windows NT 4.0 from Microsoft Corporation of Redmond, Wash. The processors 12a, 12b each include a plurality of internal registers 13a, 13b and interrupts 14a, 14b, respectively, including a system management interrupt ("SMI"). The processors 12a, 12b each connect to a local bus 15 for accessing one or more components, including a chipset 16. The chipset 16 serves as an interface for accessing other components such as a main memory 18 and a video card 20.

The chipset 16 may, for example, be a 440 BX chipset produced by Intel, Corp., and the main memory 18 may be a single shared memory. Alternatively, the memory 18 may be segregated for each processor. The chipset 16 further interconnects the local bus 15, the video card 20, and the memory 18 with one or more peripheral buses, such as a PCI bus 22. The PCI bus 22, in turn, further connects with an industry standard architecture ("ISA") bus 24, an integrated drive electronics ("IDE") bus 26, and USBs 28a, 28b as described in greater detail below.

The PCI bus 22 connects to one or more peripheral devices, such as a network interface card 30, and may connect to even more devices through one or more PCI ports 32. Similarly, the ISA bus 24 connects to one or more peripheral devices, such as a storage of basic input/output system ("BIOS") code 34 and may connect to even more devices through one or more ISA ports 36. The IDE bus 26 also connects to one or more peripheral devices, such as a hard disk drive 38. The USBs 28a, 28b may connect to any number of components, such as a USB keyboard 29, through one or more of the ports 40a, 40b, respectively.

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