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Analog Bits Unveils Industry’s Lowest Power 40nm High Bandwidth SerDes

MOUNTAIN VIEW, Calif. Feb. 7, 2011 Ser Des

The Analog Bits 40nm SerDes supports more than 100 lanes, from 1 to 12.5 Gb per lane, on single IC with a mere 5mw per gigabit per second per lane power consumption.  It is currently in production in multiple applications and is validated in over 30 industry standard protocols including PCI Express, SATA, XAUI, XFI, SGMII, and delivers the lowest chip-to-chip communications latency.  

Mahesh Tirupattur

The Path to the Future

SerDes technology converts between parallel and serial communications protocols and is of increasing importance in embedded SoC applications.  

Rich Wawrzyniak


Mahesh Tirupattur


[email protected]

SOURCE Analog Bits, Inc.

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