High-Performance SerDes IP Platform Supports 10GBase-KR, CEI-11G, PCIe 3.0, SATA 6G and Other Key IO Standards Up to 12.5Gb/s
The new platform, which is capable of supporting a number of different high-speed serial standards, includes a number of architectural changes to improve performance while adjusting to the design challenges of the 28 nanometer node. The new MS PHY, operates at speeds up to 12.5Gb/s and at 7.2mw per Gb/s of power per channel in a quad configuration. The silicon footprint is small, while maintaining margin for yield.
Support for Multiple Standards
The Snowbush MS PHY IP operates at speeds ranging from 1Gb/s to over 12Gb/s. Supported standards include:
- Ethernet for 10GBase-KR, BASE-R, XFI, RXAUI and XAUI
- Optical Interface Forum (OIF) for CEI-11G and CEI6G
- PCI-SIG for PCIe 3,2, and 1
- USB 3.0
- SATA and SAS at 1.5Gb/s, 3Gb/s and 6Gb/s and is positioned to handle the new emerging SATA standards at 12Gb/s
The new MS PHY features new digital control for programming the SerDes to support different standards. Digital calibration and trimming tune the performance of the PHY and adaptation functionality adjusts to varied channel characteristics to ensure the best quality of service on the link. Auto-negotiation and link training are provided for standards requiring those features.
In addition to exceeding the performance requirements of the targeted standards, the new Snowbush MS PHY is highly programmable and optimized for low power and minimal silicon footprint. The low power transmit driver is immune to supply noise while delivering amplitude and slew rate programmability as well as multi-tap pre- and post-emphasis. On the receive side, a best-in-class Continuous Time Linear Equalizer (CTLE) with Automatic Gain Control (AGC) feeds a 5-tap Decision Feedback Equalizer (DFE) to minimize Inter Symbol Interference (ISI) and deliver optimized eye data. The MS PHY supports a number of different power management modes including allowing each lane to be powered-down independently.
A number of test and debug features are available including an on-chip EyeView-Scope-on-a-Chip™ eye monitor for accurate visibility of the input signal quality and performance of the equalization, Pseudo Random Bit Sequence (PRBS) generators/checkers with a User Defined pattern option, and jitter injection. AC JTAG is also available.
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