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Latest Release of Synopsys IC Compiler Delivers Faster Design Closure

MOUNTAIN VIEW, Calif. Jan. 31, 2011

Brad Howe

Power-sensitive designers have access to a powerful leakage optimization engine integrated in IC Compiler. Recommended for final-stage leakage recovery on a close-to-tapeout design, this engine is architected to deal with a multitude of cell variants to deliver optimal leakage reduction while preserving timing. This release also delivers up to 10 percent lower out-of-the-box clock tree power and a 10 percent reduction in total buffer count for reduced dynamic power consumption. Additional QoR improvements include advances in clock feasibility, signal integrity and electro-migration closure.

The IC Compiler 2010.12 release continues to improve runtime performance, delivering an additional 1.5X speed-up along with a 20 percent reduction in memory. On-Demand Loading technology (ODL), first introduced to significantly reduce time-to-floorplan creation, has been extended to top-level closure to accelerate turnaround-time by 2X to 3X.  Using ODL, concurrent optimization of top and block interfaces enables blocks to be adjusted transparently, reducing the need for costly feedback loops between top-level and block-level implementation. IC Compiler In-Design physical verification technology dramatically reduces design iterations by enabling signoff-accurate DRC analysis and repair during design. In this release, incremental revalidation of repair regions and improved fix rates result in up to 7X faster automatic DRC repair times.  

Antun Domic

About Synopsys

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Synopsys and Galaxy are registered trademarks or trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

Editorial Contacts:

Sheryl Gulizia

Synopsys, Inc.


[email protected]

Lisa Gillette-Martin

MCA, Inc.

650-968-8900 ext. 115

[email protected]

SOURCE Synopsys, Inc.

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