BARCELONA, Spain Feb. 14, 2011
The ACP3423 represents the next generation of communication processors built using the LSI asymmetric multicore architecture. The ACP3423 communication processor supports Synchronous Ethernet, which is critical for high-accuracy frequency synchronization for base-station and cell-site equipment deployed in all-IP/Ethernet networks. The ACP3423 also supports IEEE1588v2 timing-over-packet timing synchronization.
Through rapid feature optimization enabled by the underlying SoC architecture, ACP3423 is projected to achieve up to 35% in power dissipation reduction as compared to the performance optimized ACP3448 while delivering up to 10Gb/s of wirespeed performance. The processor is pin and software compatible with the other members of the Axxia family and is also available in a reduced pin-count package that minimizes board space. Software compatibility across the Axxia family allows customers to leverage existing designs and minimize time-to-market for newer products.
The ACP3423 communication processor features two PowerPC® 476FP processor cores running up to 1.6GHz and a wide array of intelligent offload engines, including industry-leading packet classification, traffic management, security processing and deep packet inspection. The asymmetric multicore architecture at the heart of the Axxia family allows for processing huge volumes of wireless traffic through the offload engines, enabling low-latency, fast-path processing with no load on the CPU complex. The on-chip processing elements are tied together using the LSI Virtual Pipeline™ technology, which delivers deterministic performance under varying traffic loads. The ACP3423 communication processor includes one XAUI and eight SGMII ports as well as PCIe® and sRIO® interfaces.
Barcelona, Spain February 14 to 17
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SOURCE LSI Corporation