For managing silicon variability and reducing leakage power, Open-Silicon offers VariMAX with back biasing. Open-Silicon’s 28nm development efforts have shown back biasing to be effective at dramatically reducing leakage power even with new high-K metal gate (HKMG) transistors. As low-power design moves to the mainstream, back biasing is becoming a critical technology for maximizing yields for high-volume mobile SoCs and managing power density for high-performance networking and computing silicon.
Open-Silicon offers PowerMAX for low-power design. In particular, Multi-Threshold CMOS (MTCMOS) has been used in many designs across multiple foundries. With MTCMOS, Open-Silicon has efficiently implemented block-level power gating using either header or footer cells as well as memory retention, state retention flops, level shifters, isolation cells and rush current analysis.
design-lite model Colin Baldwin
About Open-Silicon, Inc.
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