MOUNTAIN VIEW, Calif. April 30, 2012
Samsung fabricated the three–million-instance, dual-core Cortex-A15 processor on a 32LP high-K metal gate (HKMG) process. Synopsys collaborated closely with SARC on an implementation methodology based on key high performance technologies and optimization techniques in the Galaxy Implementation Platform to meet Samsung’s stringent mass production criteria for an on-time tapeout. The processor core relied on Physical Datapath in Design Compiler® Topographical and IC Compiler for the structured placement of registers to meet power and area objectives. Layout-based debug with Design Compiler Topographical allowed quick analysis of library, netlist and placement issues to close timing. Clock mesh in IC Compiler and PrimeTime® provided the low skew and increased on-chip-variation (OCV) tolerance necessary for the high-performance core.
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SOURCE Synopsys, Inc.