BOSTON February 10, 2011
As SoC designs increase in complexity to deliver the enhanced features required by today’s mobile consumer, designers face the challenge of continuing to reduce the voltage while maintaining the stability of the SRAM bit-cells. Early benchmarks on FD-SOI technology demonstrate the ability to reduce the SRAM operating voltage by 100-150mV, thereby reducing memory power consumption up to 40 percent while maintaining the stability of the SRAM.
Using an ARM Cortex(TM) processor as a prototyping vehicle, a team of SOI Industry Consortium members demonstrated that planar FD-SOI technology enables designers to continue to decrease the voltage to reduce the overall power, while maintaining system performance.
The inherent benefits of FD-SOI can also significantly improve system performance as you transition from generation to generation. Traditionally, low-power manufacturing technology processes from one generation node to another yield a performance gain ranging from 20 percent to 30 percent. This assessment indicates that when the same transition also includes FD-SOI technology an additional 80 percent gain can be achieved beyond the traditional increase. This level of improvement can enable higher-performance handheld products while significantly reducing the overall system power, which translates into a superior user experience.
FD-SOI also provides a compelling manufacturing advantage compared to other potential solutions. Due to its advanced starting substrate, FD-SOI wafer processing is simpler for the chip manufacturer. The elimination of a considerable number of mask layers during transistor-formation processing drives simpler manufacturing process flow, and thereby a cost-efficient approach to further shrinking CMOS transistors.
SOI, recognized as a green semiconductor technology, has been in high-volume manufacturing for over a decade, enabling high-performance computing, gaming and communications products, with hundreds of millions of SOI chips shipped. FD-SOI also allows for full design re-usability: all established design tools and methodologies are fully implementable. SOI wafer manufacturers have affirmed that the ultra-thin SOI wafers needed for FD-SOI meet all specifications and are ready for high-volume manufacturing.
About the SOI Industry Consortium:
Ritsumeikan University Stanford University University of California-Berkeley http://www.soiconsortium.org
The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions.
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SOURCE The SOI Industry Consortium