The production-ready Lynx Design System provides design teams with a comprehensive design environment, including:
- An open, advanced production flow based on the Synopsys Galaxy™ Implementation Platform
- A Foundry-Ready System technology plug-in pre-validated for CPA 28-nm HKMG technology to accelerate project start and tape-out
- Advanced visualization capabilities for managing chip design that enable easy flow configuration and execution, as well as on-demand project metrics
The Lynx Design System takes full advantage of the latest Galaxy enhancements, including:
- Low power implementation flow including concurrent multi-corner, multi-mode (MCMM) optimization and analysis with support for IEEE 1801 standard
- Design Compiler® Graphical physical guidance to IC Compiler that tightens timing and area correlation for a faster, predictable and convergent path from RTL to GDSII
- IC Compiler Zroute DFM-optimized router and In-Design DRC auto fixing with IC Validator, dynamic rail analysis with PrimeRail, and final stage leakage reduction that preserves timing
The Foundry-Ready System technology plug-in for CPA 28-nm technology provides:
- Scripts, templates and documentation based on Lynx’s pre-validated production design flow, using 28-nm HKMG foundry technology files and ARM Artisan standard cell logic and memory physical IP, to expedite project setup and design start
- Baseline process-specific methodologies, representative settings, design checks and guidelines that speed design closure and tape-out to CPA foundries
The ARM Artisan™ Physical IP platform for the Common Platform CPA 28-nm technology process provides the fundamental building blocks to implement high performance, low power SoCs. ARM’s silicon proven IP platform offers a comprehensive set of memory compilers, standard cells/logic and general purpose IO (GPIO) products that meet the most demanding performance and power requirements of the mobile communication and computing markets.
The Lynx Design System also provides an environment for full SoC integration of processors, peripherals and interface IP, including:
- High performance, low power-optimized implementation for the ARM Cortex-A9 MPCore™ processor. This multicore processor delivers increased performance, scalability and increased control over power consumption for high-performance networking, auto-infotainment, mobile and consumer applications.
- Synopsys DesignWare interface IP, including the USB 2.0 On-the-Go (OTG), HDMI 1.4 and DDR 3/2 PHYs for CPA 28-nm LP technology. These PHYs are optimized for area and low power, and designed to compensate for process, voltage and temperature variations, targeting mobile and consumer applications.
Common Platform Technology Forum Santa Clara Tuesday, January 18 4:30pm
Mountain View, California North America Europe Japan Asia India http://www.synopsys.com
Forward Looking Statements
October 31, 2010
Synopsys, Design Compiler, DesignWare and Galaxy are trademarks or registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
ARM is a registered trademark of ARM Limited. Artisan, Cortex, MPCore and DesignStart are trademarks of ARM Limited.
SOURCE Synopsys, Inc.