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Synopsys Collaborates with Industry Consortium on Solutions to Model Latest 28-nm Parasitic Effects

MOUNTAIN VIEW, Calif. Feb. 1, 2011

Bari Biswas

The new IMTAB ratified extensions to ITF include:

  • Device conductor layer type specification to define a conductor’s function based on the geometric characteristics
  • High-k gate oxide thickness and dielectric constant specification for accurate capacitance calculation
  • 2-dimensional table to model rectangular via etch as a function of length and width
  • Area-dependent temperature coefficient table for accurate via resistance calculation
  • Model format to describe through-silicon via (TSV) for on-chip extraction to support 3-dimensional IC and silicon interposer design methodologies

Peter Lefkin

Wednesday, March 23, 2011

IEEE-ISTO [email protected]

About ITF

Synopsys’ Interconnect Technology Format (ITF) provides detailed modeling of interconnect parasitic effects that enables designers to perform accurate parasitic extraction for timing, signal integrity, power and reliability signoff analysis. ITF offers a flexible and innovative format to accurately model the effects of increased process variation at advanced process technologies. ITF has been evolving for more than 10 years and is the semiconductor industry’s most widely used interconnect modeling format; proven on thousands of production designs. It is supported by leading semiconductor foundries, integrated device manufacturers, and EDA tool providers.


About Synopsys

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Synopsys and TAP-in are registered trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

Editorial Contacts:

Sheryl Gulizia

Synopsys, Inc.


[email protected]

Lisa Gillette-Martin

MCA, Inc.

650-968-8900 ext. 115

[email protected]

SOURCE Synopsys, Inc.

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