Latest News

Synopsys’ DesignWare DDR PHY Compiler Eases Integration of Memory Interface IP

MOUNTAIN VIEW, Calif. Jan. 26, 2011

Keh-Ching Huang

Supporting the DesignWare DDR2/3-Lite, DDR 3/2 and DDR multiPHY IP products, the DesignWare DDR PHY compiler’s GUI steps the user through a series of decisions as they construct their DDR PHY from hard IP components, including application-specific DDR I/Os. Designers have control over multiple variables including supported DRAM types (such as DDR3, DDR2, Mobile DDR and/or LPDDR2), foundry and process node, memory channel width, power-to-signal ratios, core power requirements and other physical placement variables. The DesignWare DDR PHY compiler produces an instantly viewable image of the DDR PHY layout, a list of the pins, area, a power consumption report, placement scripts and an RTL model of the PHY.

John Koeter


DesignCon 2011 Conference February 2-3 Santa Clara Santa Clara, California


About DesignWare IP

interface IP analog IP embedded memories logic libraries audio post-processing configurable processor cores SystemC transaction-level models reuse tools

About Synopsys

Mountain View, California North America Europe Japan Asia India

Synopsys and DesignWare are registered trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

Editorial Contact:

Sheryl Gulizia

Synopsys, Inc.


[email protected]

Stephen Brennan



[email protected]

SOURCE Synopsys, Inc.

Leave a comment

seks shop - izolasyon
basic theory test book basic theory test