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Synopsys Extends HAPS Debug Visibility by 100X

MOUNTAIN VIEW, Calif. April 25, 2012


  • Combination of new Synopsys HAPS hardware and Identify software enables greater visibility of internal signals in FPGA-based prototypes to accelerate SoC design debug
  • New release provides approximately 100X more storage capacity for signal traces with sample speeds up to 60 MHz
  • Utilization of FPGA memory resources significantly reduced to better accommodate complex SoC prototyping projects


Manoj Unnikrishnan

Confirming correct functionality of high-speed interface designs often requires sampling at dozens of frequencies for several milliseconds at a time. Traditionally, designers have had to make a choice between capturing long signal trace histories that consume extensive FPGA memory resources or saving FPGA memory resources but losing detailed visibility into signal trace history. By pairing the Synopsys® Identify® Intelligent Integrated Circuit Emulator (IICE™) with a HAPS Deep Trace Debug SRAM daughter board, HAPS Deep Trace Debug allows many unique signal probes with complex triggers to be recorded and provides deeper memory to store extensive state history as the system executes. The SRAM daughter board also frees up the FPGA’s on-chip RAM for prototyping an SoC design’s memory blocks.

David Chapman

John Koeter

Availability & Resources

Identify RTL debugger

About Synopsys

Mountain View, California North America Europe Japan Asia India

Editorial Contacts:

Tess Cahayag

[email protected]

Stephen Brennan

[email protected]

SOURCE Synopsys, Inc.

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