MOUNTAIN VIEW, Calif. Jan. 31, 2011
Increasing demand for consumer electronics, like smartphones, media tablets and Internet-connected HDTVs, is driving semiconductor companies to rapidly implement massively integrated, multimillion-instance Gigascale IC designs. Thanks to the convergence of logic synthesis, physical implementation and signoff into an integrated platform, Synopsys’ Galaxy Platform delivers the scalability and throughput that are essential to implement the largest ICs, designed for the most advanced process technologies. Key components of the Galaxy Platform include:
- Design Compiler® Graphical with IC Compiler: Provides faster RTL-to-physical convergence from initial design exploration through concurrent multi-corner/multi-mode (MCMM) optimization, and closure for timing, power, testability and area;
- IC Compiler’s Zroute technology: Offers concurrent design for manufacturability (DFM) routing for advanced process technologies. Coupled with In-Design physical verification via IC Validator enables the fastest multicore, lithography-aware routing and delivers full compliance with complex DRC rules required for advanced silicon nodes; and
- PrimeTime® HyperScale technology: Speeds block-level timing closure in the context of the top-level design, dramatically accelerating signoff of complex, hierarchical designs.
Among core technology enhancements, the Galaxy 2010.12 release delivers significant runtime and capacity improvements, including:
- RTL Synthesis
- Reduction of total negative timing slack in DC Ultra™ averaging 25 percent, resulting in increased design closure predictability
- Physical Implementation
- Extended on-demand loading (ODL) technology in IC Compiler for two to three times (2-3X) faster top-level physical design closure
- Seven times (7X) faster In-Design automatic DRC repair
- Twenty percent runtime and memory improvements in PrimeTime
- New capabilities in PrimeTime to support SPICE-accurate clock mesh analysis, an essential technology required for designs with embedded processor cores
- Enhancements to PrimeTime HyperScale technology delivering runtime efficiencies for designs with multiply-instantiated blocks
- One-and-a-half times (1.5X) faster parasitic extraction with StarRC™
- New buffer tree creation and aggressive area recovery techniques result in an average 10 percent reduction in buffer and inverter cells, providing power, routability and area improvements.
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Synopsys, Galaxy, DC Ultra, Design Compiler, PrimeTime, SolvNet and StarRC are registered trademarks or trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
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SOURCE Synopsys, Inc.