SAN JOSE, Calif. Jan. 31, 2011
Expanding Xilinx’s technology foundation and product portfolio to include high level synthesis will enable the company to deliver the benefits of programmable platforms to a broader base of companies where system architects and hardware designers are accustomed to designing at a higher level of abstraction in C, C++ and System C. It will also enable Xilinx to address growing customer demand for tools that support electronic system-level (ESL) design methodologies for today’s complex designs targeted in field-programmable gate arrays (FPGAs).
"Recently, we commissioned an independent study to evaluate high-level synthesis tool offerings. Based upon benchmarks conducted by BDTI as well as Xilinx Research Labs, it was clear that AutoPilot’s quality of results matched or exceeded hand-coded RTL for data path-intensive and DSP designs. We’re delighted to welcome the AutoESL team to Xilinx. Together, I have every confidence we’ll deliver on the promise of FPGA-based electronic system-level design."
Cupertino, California Beijing, China
Jeff Bier Xcell Journal
"Development time has been a key impediment for many system designers trading off the use of a programmable DSP processor vs. an FPGA. Our evaluation indicates that this new approach involving high-level synthesis tools largely eliminates this barrier for applications, such as the BDTI Optical Flow Workload."
About the AutoPilot High Level Synthesis Tool for Xilinx FPGAs
The AutoPilot high level synthesis tool is optimized for Xilinx FPGA architectures and intelligently generates register transfer-level (RTL) code that produces the best possible QoR to meet throughput, power, area and timing design goals. It also reduces verification time by orders of magnitude due to the advantage of working at a higher level of abstraction in C, C++ or SystemC.
Xilinx’s new Virtex®-7 family of devices provides up to 2M logic cells and 4000 DSP48E1 slices. The combination of AutoPilot high level synthesis and plug-and-play IP will reduce development time for customers who model in C, C++ or SystemC.
With high level synthesis, embedded designers using Xilinx’s new Extensible Processing Platform will be able to more seamlessly partition designs between the ARM® Cortex™-A9 MPCore processor and the programmable logic. The combination of AutoPilot and ISE® Design Suite will enable system architects, hardware designers and, in the future, embedded software developers to apply a combination of serial and parallel processing to address the challenging system requirements presented by the global demand for embedded systems to perform increasingly complex functions.
About the Xilinx Platform Strategy
Given the sophistication of today’s programmable platforms and diverse set of application requirements Xilinx serves, it is no longer feasible for a single design flow or environment to fit every designer’s need. System designers, algorithm designers, software coders, and logic designers each represent a different user profile or persona with unique requirements for a design methodology and associated design environment.
Rather than providing fixed tools, Xilinx strategy is to match each user profile to a preferred methodology and design flow. At the system-level, C, C++, SystemC, and MATLAB® are most widely used, as the level of design abstraction moves up from HDL (VHDL/Verilog) at the component level.
The result is a methodology and complete design flow tailored to each user profile for design creation, design implementation, and design verification. Altogether, plug-and-play IP, targeted reference designs, development boards, design services and support from the Alliance Program ecosystem create a powerful foundation for customers to fully exploit the benefits of Xilinx programmable platforms.
About AutoESL Design Technologies, Inc.
UCLA Cupertino, California Beijing, China www.autoesl.com
the United States
SOURCE Xilinx, Inc.