SAN JOSE, Calif. April 24, 2012
interconnect-based Virtex®-7 devices Victor Peng
To address integration bottlenecks, the Vivado IDE includes electronic system level (ESL) design tools for rapidly synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems with 3X faster simulation, while hardware co-simulation provides 100X more performance.
To address implementation bottlenecks, Vivado tools include a hierarchical device editor and floor planner, a 3-15X faster logic synthesis tool with industry leading support for SystemVerilog, and a 4X faster, more deterministic place and route engine that uses analytics to minimize a ‘cost’ function of multiple variables such as timing, wire length and routing congestion. In addition, incremental flows allow for engineering change order (ECO) induced changes to be quickly processed by only re-implementing a small part of the design, while preserving performance. Finally, leveraging the new shared scalable data model, the tools provide power, timing and area estimates at every stage of the design flow, enabling up front analysis and then optimization with integrated capabilities such as automated clock gating.
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April 24, 2012
Since Xilinx began working on the Vivado Design Suite four years ago, it has engaged with hundreds of Xilinx Alliance Program members and customers to bring the tools to a mature state for release. Each has played a role in helping to ensure that Xilinx has built a highly productive set of tools for breaking through integration and implementation bottlenecks as customers design their next generation ‘All-Programmable’ devices. Here’s what some of them have to say about the Vivado Design Suite.
– Luc Burgun, CEO, President and Founder
– Sachin Vaish, Engineering Manager
– John Bobyn, Vice President, Engineering
– Mark Wagner, Senior Design Engineer
– Yasuo Hatsumi, Vice President
– Gordan Galic, Technical Marketing Manager
– Allen Vexler, CTO
– Steve McDonald, Director
– Simon Robin, President
– Endric Schubert, CTO
– Yasuo Yamamoto, IP Platform Business Unit Leader
– Roger Fawcett, Managing Director
– Justin Braun, FPGA Design Manager
– Shakeel Jeeawoody, Director of Product Marketing
– Nick Sgoupis, Senior Principal Engineer
– Mukul Gadde, Design Engineer
Katty Van Mele
– Omid Sojoodi, Director of LabVIEW FPGA and Real-Time
– Stephane Hauradou, CTO
– John Koeter, Vice President of Marketing for IP
– Piyush Sancheti, Sr. Director, Business Development
SOURCE Xilinx, Inc.