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Xilinx Unveils the Vivado Design Suite for the Next Decade of ‘All Programmable’ Devices

SAN JOSE, Calif. April 24, 2012

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interconnect-based Virtex®-7 devices Victor Peng


AMBA4 AXI4

To address integration bottlenecks, the Vivado IDE includes electronic system level (ESL) design tools for rapidly synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems with 3X faster simulation, while hardware co-simulation provides 100X more performance.

To address implementation bottlenecks, Vivado tools include a hierarchical device editor and floor planner, a 3-15X faster logic synthesis tool with industry leading support for SystemVerilog, and a 4X faster, more deterministic place and route engine that uses analytics to minimize a ‘cost’ function of multiple variables such as timing, wire length and routing congestion. In addition, incremental flows allow for engineering change order (ECO) induced changes to be quickly processed by only re-implementing a small part of the design, while preserving performance. Finally, leveraging the new shared scalable data model, the tools provide power, timing and area estimates at every stage of the design flow, enabling up front analysis and then optimization with integrated capabilities such as automated clock gating.

Paul Rolfe


Vivado Design Suite Zynq™-7000 ISE Design Suite www.xilinx.com/design-tools


www.xilinx.com

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April 24, 2012

Since Xilinx began working on the Vivado Design Suite four years ago, it has engaged with hundreds of Xilinx Alliance Program members and customers to bring the tools to a mature state for release. Each has played a role in helping to ensure that Xilinx has built a highly productive set of tools for breaking through integration and implementation bottlenecks as customers design their next generation ‘All-Programmable’ devices. Here’s what some of them have to say about the Vivado Design Suite.

EVE, Hardware/Software Co-Verification

– Luc Burgun, CEO, President and Founder

CoreEL Technologies, Premier Xilinx Alliance Program Member

– Sachin Vaish, Engineering Manager

Fidus Systems, Inc., Premier Xilinx Alliance Program Member
North America

– John Bobyn, Vice President, Engineering

Northwest Logic, Premier Xilinx Alliance Program Member

– Mark Wagner, Senior Design Engineer

Tokyo Electron Device Ltd., Premier Xilinx Alliance Program Member

– Yasuo Hatsumi, Vice President

Xylon d.o.o., Premier Xilinx Alliance Program Member
"

– Gordan Galic, Technical Marketing Manager

A2e Technologies, Certified Xilinx Alliance Program Member

– Allen Vexler, CTO

Aliathon, Ltd., Certified Xilinx Alliance Program Member

– Steve McDonald, Director

Hardent Inc., Certified Xilinx Alliance Program Member

– Simon Robin, President

Missing Link Electronics, Certified Xilinx Alliance Program Member

– Endric Schubert, CTO

Oki Information Systems Co., Certified Xilinx Alliance Program Member

– Yasuo Yamamoto, IP Platform Business Unit Leader

OmniTek Ltd., Certified Xilinx Alliance Program Member

– Roger Fawcett, Managing Director

4DSP, Inc., Xilinx Alliance Program Member

– Justin Braun, FPGA Design Manager

Blue Pearl Software, Inc., Xilinx Alliance Program Member

– Shakeel Jeeawoody, Director of Product Marketing

CAST, Inc., Xilinx Alliance Program Member

– Nick Sgoupis, Senior Principal Engineer

Great River Technology, Inc., Xilinx Alliance Program Member

– Mukul Gadde, Design Engineer

IntoPix s.a., Xilinx Alliance Program Member

Katty Van Mele

National Instruments Corp., Xilinx Alliance Program Member

– Omid Sojoodi,  Director of LabVIEW FPGA and Real-Time

PLDA, Xilinx Alliance Program Member

– Stephane Hauradou, CTO

Synopsys, Inc., Xilinx Alliance Program Member

– John Koeter, Vice President of Marketing for IP

Atrenta, Inc., Xilinx Alliance Program Member

– Piyush Sancheti, Sr. Director, Business Development


Bruce Fienberg

[email protected]

SOURCE Xilinx, Inc.

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